Many processors control input/output (“I/O”) devices use a memory-mapped I/O scheme that enables a processor to communicate to an I/O device by reading and writing to one or more memory addresses reserved for that particular I/O device. The data and the addresses storing that data are generally characterized by the manner in which the data is cached for specific I/O devices, such as “uncacheable” memory, “prefetchable” memory “write-combined” memory, “write-through” memory, “write-back” memory, “write-protect” memory, and the like. A drawback of this approach, however, is that the memory addresses reserved for each I/O device reduces system memory available to the processor. Collectively, those reserved addresses constitute a “memory hole,” which is a term commonly used to describe the address space memory that is inaccessible to a processor as a DRAM. Further, as the number of I/O devices increases, the amount of memory available to that processor as a DRAM decreases correspondingly. To illustrate the effects of memory holes on system memory, consider a 32-bit processor having access up to 4 GB of memory (i.e., an amount of memory including 232 addresses) and being a part of a computing system having four graphics processing units (“GPUs”) as I/O devices. Usually, each of these GPUs can require 512 megabytes (MB) of address space (i.e., an amount of memory including 229 addresses) in system memory to maintain frame buffers, which would then require reserving a total amount of 2 gigabytes (“GB”) of address space to cover all four GPUs. Moreover, additional system memory must be dedicated for boot code and for other I/O devices, such as audio and visual devices. Consequently, the processor of this example would have less than one-half of its system memory available to perform its computational tasks. So if reserved memory were to expand without bound, processors would be left without much system memory with which to operate.
There are several memory addressing techniques known for redirecting accesses from one range of addresses of memory to another range of addresses. Some of these techniques are used for reducing the effects of memory holes, while others are directed toward other memory management functions.
FIG. 1 illustrates one memory addressing technique used for ameliorating the effects of memory holes. In this approach, system memory 100 is increased by adding extended memory 102 to the normal amount of memory available that is useable to a processor (“useable memory”) 108, which typically is about 640 kilobytes (“KB”). By adding extended memory 102, system memory 100 recovers the 384 KB of system memory usually lost to memory hole 104. In this memory addressing technique, an arithmetic operator 106 adds an amount, “delta,” to a linear address (“LA”) 101 to form adjusted address 103 (i.e., LA+delta), but only if address 101 is above 640 KB. Arithmetic operator 106 therefore redirects address 101 from a reserved address space in memory hole 104 to the supplemental address space in extended memory 102. While functional, adding an amount “delta” to an address is relatively cumbersome in execution and requires more hardware to implement adders than otherwise is necessary to reduce the effects of memory holes.
In another conventional memory addressing technique, a first frame buffer within a memory hole is separately remapped at a number of memory locations from a second frame buffer. By remapping the first frame buffer as an instance of memory at a relatively large distance from the second one, these two frame buffers will have more address space in which to expand without encroaching each other's addresses than if remapping is absent. As described above, this technique remaps addresses without supplementing system memory lost to memory holes. Furthermore, this technique is restricted to remapping addresses only within a memory hole. But with this technique, logical operators such as AND and OR logic functions replace addition to redirect memory accesses. By using logic gates to implement the logical operators, fewer hardware resources are required than would be necessary if adders, such as arithmetic operator 106, are used. Nonetheless, the logic gates used to implement this conventional memory technique introduces an amount of delay that is longer than otherwise is necessary.
In view of the foregoing, it would be desirable to provide a system, an apparatus and a method for minimizing the drawbacks of the above-mentioned memory addressing techniques in the reclamation of memory that otherwise would be lost to a memory hole.